Frequency divider
A frequency divider is an electronic circuit that takes an input signal with a frequency, fin, and generates an output signal with a frequency:
The feedback signal is fin / 2. This produces sum and difference frequencies fin / 2, 3fin / 2 at the output of the mixer. A low pass filter removes the higher frequency and the fin / 2 frequency is amplified and fed back into mixer.
Steady state examination seems simple enough however startup is more complicated. In order to establish a stable 1/2 frequency feedback, the amplifier gain at the half frequency must be greater than unity. The phase shift must also be an integer multiple of 2pi.
For power-of-2 integer division, a simple binary counter can be used, clocked by the input signal. The least-significant output bit alternates at the same rate as the input, the next bit is the 1/2 the rate, the third bit is 1/4 the rate, etc. An arrangement of flipflops are a classic method for integer-n division. Such division is frequency and phase coherent to the source over environmental variations including temperature. The easiest configuration is a series where each flip-flop is a divide-by-2. For a series of three of these, such system would be a divide-by-8. By adding additional logic gates to the chain of flip flops, other division ratios can be obtained. Integrated circuit logic families can provide a single chip solution for some common division ratios.
An arrangement of D flip-flops are a classic method for integer-n division. Such division is frequency and phase coherent to the source over environmental variations including temperature. The easiest configuration is a series where each D flip-flop is a divide-by-2. For a series of three of these, such system would be a divide-by-8. More complicated configurations have been found that generate odd factors such as a divide-by-5. Standard, classic logic chips that implement this or similar frequency division functions include the 7456, 7457, 74292, and 74294. (see List of 7400 series integrated circuits)
http://en.wikipedia.org/wiki/Frequency_divider
Rooselvet Ramirez CAF
Analog dividers
Regenerative frequency divider
A regenerative frequency divider, also known as a Miller frequency divider, mixes the input signal with the feedback signal from the mixer.
Steady state examination seems simple enough however startup is more complicated. In order to establish a stable 1/2 frequency feedback, the amplifier gain at the half frequency must be greater than unity. The phase shift must also be an integer multiple of 2pi.
Injection-locked frequency divider
Main article: Injection locked frequency divider
A free-running oscillator which has a small amount of a higher-frequency signal fed to it will tend to oscillate in step with the input signal. Such frequency dividers were essential in the development of television.Digital dividers
To divide a digital signal by an integer multiple a Johnson counter is used. This is a type of shift register network that is clocked by the input signal. The last register's complemented output is fed back to the first register's input. The output signal is derived from the combination of the register outputs. For example, a divide-by-3 divider can be constructed with a 3-register Johnson counter. The three valid values for each register are 000, 100, 110, 111, 011, and 001. This pattern repeats each time the network is clocked by the input signal. The values 000 and 111 occur three clock pulses apart and control the state change of the output signal. Additional registers can be added to provide additional integer divisors.For power-of-2 integer division, a simple binary counter can be used, clocked by the input signal. The least-significant output bit alternates at the same rate as the input, the next bit is the 1/2 the rate, the third bit is 1/4 the rate, etc. An arrangement of flipflops are a classic method for integer-n division. Such division is frequency and phase coherent to the source over environmental variations including temperature. The easiest configuration is a series where each flip-flop is a divide-by-2. For a series of three of these, such system would be a divide-by-8. By adding additional logic gates to the chain of flip flops, other division ratios can be obtained. Integrated circuit logic families can provide a single chip solution for some common division ratios.
Mixed signal division
(Classification: asynchronous sequential logic)An arrangement of D flip-flops are a classic method for integer-n division. Such division is frequency and phase coherent to the source over environmental variations including temperature. The easiest configuration is a series where each D flip-flop is a divide-by-2. For a series of three of these, such system would be a divide-by-8. More complicated configurations have been found that generate odd factors such as a divide-by-5. Standard, classic logic chips that implement this or similar frequency division functions include the 7456, 7457, 74292, and 74294. (see List of 7400 series integrated circuits)
Fractional-n dividers
Main article: Dual-modulus prescaler
A fractional-n frequency synthesizer can be constructed using two integer dividers, a divide-by-n and a divide-by-(n + 1) frequency divider. With a modulus controller, n is toggled between the two values so that the VCO alternates between one locked frequency and the other. The VCO stabilizes at a frequency that is the time average of the two locked frequencies. By varying the percentage of time the frequency divider spends at the two divider values, the frequency of the locked VCO can be selected with very fine granularity.Delta-sigma fractional-n synthesizers
If the sequence of divide by n and divide by (n + 1) is periodic, spurious signals appear at the VCO output in addition to the desired frequency. Delta-sigma fractional-n dividers overcome this problem by randomizing the selection of n and (n + 1), while maintaining the time-averaged ratios.http://en.wikipedia.org/wiki/Frequency_divider
Rooselvet Ramirez CAF
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