Frequency Division

Frequency Division

In the Sequential Logic tutorials we saw how D-type Flip-Flop´s work and how they can be connected together to form a Data Latch. Another useful feature of the D-type Flip-Flop is as a Binary Divider, a Frequency Divider or as a "divide-by-2" counter. Here the inverted output terminal Q (NOT-Q) is connected directly back to the Data input terminal D giving the device "feedback" as shown below.

Divide-by-2 Counter

It can be seen from the frequency waveforms above, that by "feeding back" the output from Q to the input terminal D, the output pulses at Q have a frequency that are exactly one half (f/2) that of the input clock frequency. In other words the circuit produces Frequency Division as it now divides the input frequency by a factor of two (an octave). This then produces another type of device that can best be described as a "Toggle" or "T-type" flip-flop as it toggles from one state to the next, (HIGH to LOW or LOW to HIGH) at every clock cycle and simple frequency divider circuits can easily be constructed using standard flip-flop circuits.

Toggle Flip-Flop

Another type of device that can be used for frequency division is the T-type or Toggle flip-flop. The toggle flip-flop is basically a JK-type flip-flop with its inputs tied together resulting in a device with only two inputs, the "Toggle" input itself and the controlling "Clock" input. If we connect together in series, two T-type flip-flops the initial input frequency will be "divided-by-two" by the first flip-flop (f/2) and then "divided-by-two" again by the second flip-flop ((f/2)/2), giving an output frequency which has effectively been divided four times, then its output frequency becomes one quarter value (25%) of the original clock frequency, (f/4). Each time we add another toggle or "T-type" flip-flop the output clock frequency is halved or divided-by-2 again and so on, giving an output frequency of 2ⁿ where "n" is the number of flip-flops used in the sequence.

Then the Toggle or T-type flip-flop is an edge triggered divide-by-2 device based upon the standard RS-type flip flop. They can be triggered to switch on either the leading or trailing edge of the input clock signal.

Divide-by-8 Counter

This type of counter is commonly known as an Asynchronous 3-bit Binary Counter as the output on QA to QC, which is 3 bits wide, is a binary count from 0 to 7 for each clock pulse, with the output of one flip-flop stage providing the clocking signal for the next flip-flop stage. This arrangement is commonly known as Asynchronous as each clocking event occurs independently. As the counter counts sequentially in an upwards direction from 0 to 7 this type of counter is also known as an "up" or "forward" counter (CTU) or a "3-bit Asynchronous Up Counter". Asynchronous "Down" counters (CTD) are also available

Truth Table for a 3-bit Asynchronous Up Counter

Clock Cycle	Output bit Pattern
	QC	QB	QA
0	0	0	0
1	0	0	1
2	0	1	0
3	0	1	1
4	1	0	0
5	1	0	1
6	1	1	0
7	1	1	1

Any number of flip-flops can be connected or "cascaded" together to form a "divide-by-n" binary counter where "n" is the number of counter stages used and which is generally called the Modulus. The modulus or simply "MOD" of a counter is the number of output states the counter goes through before returning itself back to zero, ie, one complete cycle. A counter with three flip-flops like the circuit above will count from 0 to 7 ie, 2^n-1. It has eight different output states representing the decimal numbers 0 to 7 and is called a Modulo-8 or MOD-8 counter. A counter with four flip-flops will count from 0 to 15 and is therefore called a Modulo-16 counter and so on.

An example of this is given as.

•   3-bit Binary Counter = 2³ = 8 (modulo-8 or MOD-8)
•  
•   4-bit Binary Counter = 2⁴ = 16 (modulo-16 or MOD-16)
•  
•   8-bit Binary Counter = 2⁸ = 256 (modulo-256 or MOD-256)

The Modulo number can be increased by adding more flip-flops to the counter. Then the modulo or MOD number can simply be written as: MOD number = 2ⁿ

4-bit Modulo-16 Counter

Multi-bit asynchronous counters connected in this manner are also called "Ripple" counters or ripple dividers because the change of each stage appears to "ripple" itself through the counter from the LSB output to its MSB output connection. Ripple counters are available in standard IC form, from the 74LS393 Dual 4-bit counter to the 74HC4060, which is a 14-bit ripple counter with its own built in clock oscillator and produce excellent frequency division of the fundamental frequency. With asynchronous ripple divider circuits there is a small delay between the arrival of the clock pulse and its output due to the internal circuitry of the gate. This delay is called the Propagation Delay and in some cases can produce false output counts. In large bit ripple counter circuits the delay of all the separate stages are added together to give a summed delay at the end of the chain which is why asynchronous counters are generally not used for in high frequency counting circuits with large numbers of bits. Then, the more flip-flops that are added to an asynchronous counter the lower the maximum operating frequency becomes. To overcome the problem of propagation delaySynchronous Counters were developed.

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Rooselvet Ramirez    CAF